A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner

	A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner
	Gao Zhuo; Yang Zongren; Zhao Ying; Yang Yi; Zhang Lu; Huang Lingyi; Hu Weiwu
	2009
发表期刊	半导体学报
ISSN	1674-4926
卷号	000 期号:004 页码:104
摘要	This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage. The receiver occupies 300×500 μm2. With the novel half rate period calibration clock data recovery （CDR） circuit, the receiver consumes 52 mW power. The receiver can compensate a wide range of channel loss by combining the low power wideband programmable continuous time linear equalizer （CTLE） and decision feedback equalizer （DFE）.
关键词	接收器 CDR 有限元 Gb 校准元组 CMOS工艺时钟数据恢复
语种	英语
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/36246
专题	中国科学院计算技术研究所期刊论文_中文
作者单位	中国科学院计算技术研究所
第一作者单位	中国科学院计算技术研究所
推荐引用方式 GB/T 7714	Gao Zhuo,Yang Zongren,Zhao Ying,et al. A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner[J]. 半导体学报,2009,000(004):104.
APA	Gao Zhuo.,Yang Zongren.,Zhao Ying.,Yang Yi.,Zhang Lu.,...&Hu Weiwu.(2009).A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner.半导体学报,000(004),104.
MLA	Gao Zhuo,et al."A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner".半导体学报 000.004(2009):104.