Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

doi:10.1109/TCAD.2010.2092510

	Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains
	Wu, Shianling 1,2; Wang, Laung-Terng 4; Wen, Xiaoqing 2; Jiang, Zhigang 3; Tan, Lang 5; Zhang, Yu 5; Hu, Yu 6; Jone, Wen-Ben 7; Hsiao, Michael S.8; Li, James Chien-Mo 4,9; Huang, Jiun-Lang 4,9; Yu, Lizhen 5
	2011-03-01
发表期刊	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
ISSN	0278-0070
卷号	30 期号:3 页码:455-463
摘要	This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered launch-on-capture (LOC) scheme followed by the one-hot LOC scheme for testing delay faults in a scan design containing asynchronous clock domains. Typically, the staggered scheme produces small test sets but needs long ATPG runtime, whereas the one-hot scheme takes short ATPG runtime but yields large test sets. The proposed hybrid technique is intended to reduce test pattern count with acceptable ATPG runtime for multi-million-gate scan designs. In case the scan design contains multiple synchronous clock domains, each group of synchronous clock domains is treated as a clock group and tested using a launch aligned or a capture aligned LOC scheme. By combining these schemes together, we found the pattern counts for two large industrial designs were reduced by approximately 1.7X to 2.1X, while the ATPG runtime was increased by 10% to 50%, when compared to the one-hot clocking scheme alone.
关键词	Aligned launch-on-capture at-speed scan testing double-capture hybrid launch-on-capture launch-on-capture one-hot launch-on-capture staggered launch-on-capture
DOI	10.1109/TCAD.2010.2092510
收录类别	SCI
语种	英语
资助项目	National Science Foundation of America[CCF-0541103] ; Japan Society for the Promotions of Science[22300017]
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Interdisciplinary Applications ; Engineering, Electrical & Electronic
WOS记录号	WOS:000287658900011
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：2[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/13177
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Wu, Shianling
作者单位	1.SynTest Technol Inc, Princeton, NJ 08550 USA 2.Kyushu Inst Technol, Dept Creat Informat, Fukuoka 8208502, Japan 3.SynTest Technol Inc, ATPG Res & Dev Grp, Sunnyvale, CA 94086 USA 4.Natl Taiwan Univ, Dept Elect Engn, Taipei 106, Taiwan 5.SynTest Technol Inc, Shanghai 201200, Peoples R China 6.Chinese Acad Sci, Inst Comp Technol, Beijing 100190, Peoples R China 7.Univ Cincinnati, Dept Elect & Comp Engn, Cincinnati, OH 45221 USA 8.Virginia Polytech Inst & State Univ, Dept Elect & Comp Engn, Blacksburg, VA 24061 USA 9.Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 106, Taiwan
推荐引用方式 GB/T 7714	Wu, Shianling,Wang, Laung-Terng,Wen, Xiaoqing,et al. Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2011,30(3):455-463.
APA	Wu, Shianling.,Wang, Laung-Terng.,Wen, Xiaoqing.,Jiang, Zhigang.,Tan, Lang.,...&Yu, Lizhen.(2011).Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,30(3),455-463.
MLA	Wu, Shianling,et al."Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 30.3(2011):455-463.