Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology

	Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology
	Hu, Wei-Wu ; Zhao, Ji-Ye ; Zhong, Shi-Qiang ; Yang, Xu ; Guidetti, Elio ; Wu, Chris
	2007
发表期刊	JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY
ISSN	1000-9000
卷号	22 期号:1 页码:1-14
摘要	This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bit-sliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.
关键词	general-purpose processor superscalar pipeline out-of-order execution non-blocking cache physical design synthesis flow bit-sliced placement crafted cell performance evaluation
收录类别	SCI
语种	英语
WOS研究方向	Computer Science
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Software Engineering
WOS记录号	WOS:000243890200001
出版者	SCIENCE CHINA PRESS
引用统计	被引频次：15[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/11062
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Hu, Wei-Wu
作者单位	1.Chinese Acad Sci, Inst Comp Technol, Key Lab Comp Syst & Architecture, Beijing 100080, Peoples R China 2.ST Microelectron, Geneva, Switzerland
推荐引用方式 GB/T 7714	Hu, Wei-Wu,Zhao, Ji-Ye,Zhong, Shi-Qiang,et al. Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology[J]. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,2007,22(1):1-14.
APA	Hu, Wei-Wu,Zhao, Ji-Ye,Zhong, Shi-Qiang,Yang, Xu,Guidetti, Elio,&Wu, Chris.(2007).Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology.JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,22(1),1-14.
MLA	Hu, Wei-Wu,et al."Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology".JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 22.1(2007):1-14.