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A hybrid hardware/software generated Prefetching Thread mechanism on Chip Multiprocessors
Rui, Hou; Zhang, Longbing; Hu, Weiwu
2006
发表期刊EURO-PAR 2006 PARALLEL PROCESSING
ISSN0302-9743
卷号4128页码:506-516
摘要This paper proposes a hybrid hardware/software generated prefetching thread mechanism on Chip Multiprocessors(CMP). Two kinds of prefetching threads appear in our hybrid mechanism. Most threads belong to Dynamic Prefetching Thread, which are automatically generated, triggered, spawn and managed by hardware; The others are of Static Prefetching Thread, targeting at the critical delinquent loads which can not be accurately or timely predicted by Dynamic Prefetching Thread. Static Prefetching Threads are statically generated by binary-level optimization tool with the guide of profiling information. Also, some aggressive thread construction policies are proposed. Furthermore, the necessary hardware infrastructure for CMP supporting this hybrid mechanism are described. For a set of memory limited benchmarks with complicated access patterns, an average speedup of 3.1% is achieved on dual-core CMP when constructing basic hardware-generated prefetching thread, and this gain grows to 31% when adopting our hybrid mechanism.
收录类别SCI
语种英语
WOS研究方向Computer Science
WOS类目Computer Science, Theory & Methods
WOS记录号WOS:000241469500045
出版者SPRINGER-VERLAG BERLIN
引用统计
文献类型期刊论文
条目标识符http://119.78.100.204/handle/2XEOYT63/10397
专题中国科学院计算技术研究所期刊论文_英文
通讯作者Rui, Hou
作者单位Chinese Acad Sci, Inst Comp Technol, Key Lab Comp Syst & Architecture, Beijing 100080, Peoples R China
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GB/T 7714
Rui, Hou,Zhang, Longbing,Hu, Weiwu. A hybrid hardware/software generated Prefetching Thread mechanism on Chip Multiprocessors[J]. EURO-PAR 2006 PARALLEL PROCESSING,2006,4128:506-516.
APA Rui, Hou,Zhang, Longbing,&Hu, Weiwu.(2006).A hybrid hardware/software generated Prefetching Thread mechanism on Chip Multiprocessors.EURO-PAR 2006 PARALLEL PROCESSING,4128,506-516.
MLA Rui, Hou,et al."A hybrid hardware/software generated Prefetching Thread mechanism on Chip Multiprocessors".EURO-PAR 2006 PARALLEL PROCESSING 4128(2006):506-516.
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