Institute of Computing Technology, Chinese Academy IR
A memory bandwidth effective cache store miss policy | |
Rui, H; Zhang, FX; Hu, WW | |
2005 | |
发表期刊 | ADVANCES IN COMPUTER SYSTEMS ARCHITECTURE, PROCEEDINGS |
ISSN | 0302-9743 |
卷号 | 3740页码:750-760 |
摘要 | Memory bandwidth becomes more and more important in the forthcoming 10 billion transistors chip times. This paper discusses and implements a memory bandwidth effective cache store miss policy. Although the write-allocate policy is adopted, we find it is possible not to load the full cache block from lower memory hierarchy when cache store miss occurs, if the cache block is fully modified before any load instruction accesses the un-modified data of the same cache block. This cache store miss policy will partly reduce the pressure on memory bandwidth, and improve the cache hit rate. We provides a hardware mechanism, Store Merge Buffer, to implement the policy in Goodson-2 processor. Our experiments demonstrate the encouraging results: Memory bandwidth improved by almost 50% (tested by stream benchmark), and IPC on SPEC CPU2K improved by 9.4% on average. |
收录类别 | SCI |
语种 | 英语 |
WOS研究方向 | Computer Science |
WOS类目 | Computer Science, Hardware & Architecture ; Computer Science, Theory & Methods |
WOS记录号 | WOS:000234508800061 |
出版者 | SPRINGER-VERLAG BERLIN |
引用统计 | |
文献类型 | 期刊论文 |
条目标识符 | http://119.78.100.204/handle/2XEOYT63/10319 |
专题 | 中国科学院计算技术研究所期刊论文_英文 |
通讯作者 | Rui, H |
作者单位 | Chinese Acad Sci, Inst Comp Technol, Beijing 100080, Peoples R China |
推荐引用方式 GB/T 7714 | Rui, H,Zhang, FX,Hu, WW. A memory bandwidth effective cache store miss policy[J]. ADVANCES IN COMPUTER SYSTEMS ARCHITECTURE, PROCEEDINGS,2005,3740:750-760. |
APA | Rui, H,Zhang, FX,&Hu, WW.(2005).A memory bandwidth effective cache store miss policy.ADVANCES IN COMPUTER SYSTEMS ARCHITECTURE, PROCEEDINGS,3740,750-760. |
MLA | Rui, H,et al."A memory bandwidth effective cache store miss policy".ADVANCES IN COMPUTER SYSTEMS ARCHITECTURE, PROCEEDINGS 3740(2005):750-760. |
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