Institute of Computing Technology, Chinese Academy IR
Improving latency tolerance of network processors through simultaneous multithreading | |
Bo, L; Hong, A; Fang, L; Rui, G | |
2005 | |
发表期刊 | ADVANCED PARALLEL PROCESSING TECHNOLOGIES, PROCEEDINGS |
ISSN | 0302-9743 |
卷号 | 3756页码:61-70 |
摘要 | Existing multithreaded network processors architecture with multiple processing engines (PEs), aims at taking advantage of blocked multithreading technique which executes instructions of different user-defined threads in the same PE pipeline, in explicit and interleave way. Multiple PEs, each of which is a multithreaded processor core, process several packets in parallel to hide long memory access latency. Most of them are optimized for throughputs mostly in data-plane. In future network workloads, the boundaries between data-plane and control-plane become blurred, so that PEs are demanded not only wire speed packet forwarding on data-plane, but also highly intelligent and increased complex packet processing function on control-plane. In this paper, we analyze SMT's short latency tolerance potential when used in out-of-order and dynamic scheduling PE cores. We show in this paper that 2-4 issue SMT provides an excellent short memory and branch latency tolerance, which gain higher instructions throughout as well as much simpler structures. |
收录类别 | SCI |
语种 | 英语 |
WOS研究方向 | Computer Science |
WOS类目 | Computer Science, Theory & Methods |
WOS记录号 | WOS:000233672200007 |
出版者 | SPRINGER-VERLAG BERLIN |
引用统计 | |
文献类型 | 期刊论文 |
条目标识符 | http://119.78.100.204/handle/2XEOYT63/10313 |
专题 | 中国科学院计算技术研究所期刊论文_英文 |
通讯作者 | Bo, L |
作者单位 | 1.Univ Sci & Technol China, Dept Comp Sci & Technol, Hefei 230026, Peoples R China 2.Chinese Acad Sci, Comp Technol Inst, Comp Architecture Lab, Beijing 100086, Peoples R China |
推荐引用方式 GB/T 7714 | Bo, L,Hong, A,Fang, L,et al. Improving latency tolerance of network processors through simultaneous multithreading[J]. ADVANCED PARALLEL PROCESSING TECHNOLOGIES, PROCEEDINGS,2005,3756:61-70. |
APA | Bo, L,Hong, A,Fang, L,&Rui, G.(2005).Improving latency tolerance of network processors through simultaneous multithreading.ADVANCED PARALLEL PROCESSING TECHNOLOGIES, PROCEEDINGS,3756,61-70. |
MLA | Bo, L,et al."Improving latency tolerance of network processors through simultaneous multithreading".ADVANCED PARALLEL PROCESSING TECHNOLOGIES, PROCEEDINGS 3756(2005):61-70. |
条目包含的文件 | 条目无相关文件。 |
个性服务 |
推荐该条目 |
保存到收藏夹 |
查看访问统计 |
导出为Endnote文件 |
谷歌学术 |
谷歌学术中相似的文章 |
[Bo, L]的文章 |
[Hong, A]的文章 |
[Fang, L]的文章 |
百度学术 |
百度学术中相似的文章 |
[Bo, L]的文章 |
[Hong, A]的文章 |
[Fang, L]的文章 |
必应学术 |
必应学术中相似的文章 |
[Bo, L]的文章 |
[Hong, A]的文章 |
[Fang, L]的文章 |
相关权益政策 |
暂无数据 |
收藏/分享 |
除非特别说明,本系统中所有内容都受版权保护,并保留所有权利。
修改评论