Wrapper scan chains design for rapid and low power testing of embedded cores

doi:10.1093/ietisy/e88-d.9.2126

	Wrapper scan chains design for rapid and low power testing of embedded cores
	Han, YH ; Hu, Y ; Li, XW ; Li, HW ; Chandra, A ; Wen, XQ
	2005-09-01
发表期刊	IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
ISSN	0916-8532
卷号	E88D 期号:9 页码:2126-2134
摘要	Connection of internal scan chains in core wrapper design (CWD) is necessary to handle the width match of TAM and infernal scan chains. However, conventional serial connection of internal scan chains incurs power and time penalty. Study shows that the distribution and high density of don't care bits (X-bits) in test patterns make scan slices overlapping and partial overlapping possible. A novel parallel CWD (pCWD) approach is presented in this paper for lowering test power by shortening wrapper scan chains and adjusting test patterns. In order to achieve shift time reduction from overlapping in pCWD, a two-phase process on test pattern: partition and fill, is presented. Experimental results on d695 of ITC2002 benchmark demonstrated the shift time and test power have been decreased by 1.5 and 15 times, respectively. In addition, the proposed pCWD can be used as a stand-alone time reduction technique, which has better performance than previous techniques.
关键词	SOC testing wrapper design scan slices overlapping
DOI	10.1093/ietisy/e88-d.9.2126
收录类别	SCI
语种	英语
WOS研究方向	Computer Science
WOS类目	Computer Science, Information Systems ; Computer Science, Software Engineering
WOS记录号	WOS:000232082000014
出版者	IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
引用统计	被引频次：1[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/10127
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Han, YH
作者单位	1.Chinese Acad Sci, Comp Technol Inst, Beijing 100080, Peoples R China 2.Chinese Acad Sci, Grad Sch, Beijing 100039, Peoples R China 3.Synopsys Inc, Mountain View, CA 94043 USA 4.Kyushu Inst Technol, Fac Comp Sci & Syst Engn, Iizuka, Fukuoka 8208502, Japan
推荐引用方式 GB/T 7714	Han, YH,Hu, Y,Li, XW,et al. Wrapper scan chains design for rapid and low power testing of embedded cores[J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS,2005,E88D(9):2126-2134.
APA	Han, YH,Hu, Y,Li, XW,Li, HW,Chandra, A,&Wen, XQ.(2005).Wrapper scan chains design for rapid and low power testing of embedded cores.IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS,E88D(9),2126-2134.
MLA	Han, YH,et al."Wrapper scan chains design for rapid and low power testing of embedded cores".IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E88D.9(2005):2126-2134.