中国科学院计算技术研究所机构知识库

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限定条件	作者：Li, Xiaowei分Li, Xiaowei    发表日期：2017

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 10, 页码: 2736-2748 作者:  Wang, Ying;  Deng, Jiachao;  Fang, Yuntan;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：53/0  |  提交时间：2019/12/12 Deep learning  error tolerance  neural network (NN)  timing variation
	Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 9, 页码: 2525-2537 作者:  Lu, Weina;  Hu, Yu;  Ye, Jing;  Li, Xiaowei 收藏  |  浏览/下载：39/0  |  提交时间：2019/12/12 Computer-aided design flow  field-programmable gate arrays (FPGAs)  hotspot optimization  performance
	Retention-Aware DRAM Assembly and Repair for Future FGR Memories 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2017, 卷号: 36, 期号: 5, 页码: 705-718 作者:  Wang, Ying;  Han, Yin-He;  Wang, Cheng;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：39/0  |  提交时间：2019/12/12 DDR  dynamic random-access memory (DRAM)  memory  refresh
	Power-Utility-Driven Write Management for MLC PCM 期刊论文 ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2017, 卷号: 13, 期号: 3, 页码: 22 作者:  Li, Bing;  Hu, Yu;  Wang, Ying;  Ye, Jing;  Li, Xiaowei 收藏  |  浏览/下载：54/0  |  提交时间：2019/12/12 Phase change memory  multi-level  main memory  power  write management  optimization
	STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 4, 页码: 1285-1296 作者:  Song, Lili;  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Cheng, Yuanqing;  Li, Xiaowei 收藏  |  浏览/下载：70/0  |  提交时间：2019/12/12 Approximate computing  machine learning  neural network  spin toque transfer RAM (STT-RAM)
	LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization 期刊论文 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2017, 卷号: E100D, 期号: 2, 页码: 323-331 作者:  Hu, Yu;  Ye, Jing;  Shi, Zhiping;  Li, Xiaowei 收藏  |  浏览/下载：52/0  |  提交时间：2019/12/12 process variation  timing variation  sample  path selection  least square