中国科学院计算技术研究所机构知识库

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限定条件	出处：IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	ApproxDup: Developing an Approximate Instruction Duplication Mechanism for Efficient SDC Detection in GPGPUs 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 4, 页码: 1051-1064 作者:  Wei, Xiaohui;  Jiang, Nan;  Yue, Hengshan;  Wang, Xiaonan;  Zhao, Jianpeng;  Li, Guangli;  Qiu, Meikang 收藏  |  浏览/下载：3/0  |  提交时间：2024/05/20 Instruction sets  Reliability  Resilience  Circuit faults  Registers  Kernel  Graphics processing units  Approximate computing  GPGPUs  instruction duplication  silent data corruptions (SDCs)  soft error
	Statistical Modeling of Soft Error Influence on Neural Networks 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 11, 页码: 4152-4163 作者:  Huang, Haitong;  Xue, Xinghua;  Liu, Cheng;  Wang, Ying;  Luo, Tao;  Cheng, Long;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：2/0  |  提交时间：2024/05/20 Fault analysis  fault simulation  neural network (NN) reliability  statistical fault modeling
	FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory Computing 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 9, 页码: 2889-2902 作者:  Liu, Rui;  Zhang, Xiaoyu;  Xie, Zhiwen;  Wang, Xinyu;  Li, Zerun;  Chen, Xiaoming;  Han, Yinhe;  Tang, Minghua 收藏  |  浏览/下载：9/0  |  提交时间：2023/12/04 Computing-in-memory (CiM)  cryptographic algorithm  ferroelectric field-effect transistor (FeFET)  instruc-tion set architecture (ISA)
	A Coordinated Model Pruning and Mapping Framework for RRAM-Based DNN Accelerators 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 7, 页码: 2364-2376 作者:  Qu, Songyun;  Li, Bing;  Zhao, Shixin;  Zhang, Lei;  Wang, Ying 收藏  |  浏览/下载：7/0  |  提交时间：2023/12/04 AutoML  bit-pruning  deep neural networks (DNNs)  resistive random access memory (RRAM)
	Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 5, 页码: 1504-1517 作者:  Mu, Jianan;  Ren, Yi;  Wang, Wen;  Hu, Yizhong;  Chen, Shuai;  Chang, Chip-Hong;  Fan, Junfeng;  Ye, Jing;  Cao, Yuan;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：9/0  |  提交时间：2023/12/04 Memory access pattern  number theoretic transform (NTT)  post-quantum cryptography (PQC)  scalable hardware design
	Variation Enhanced Attacks Against RRAM-Based Neuromorphic Computing System 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 5, 页码: 1588-1596 作者:  Lv, Hao;  Li, Bing;  Zhang, Lei;  Liu, Cheng;  Wang, Ying 收藏  |  浏览/下载：7/0  |  提交时间：2023/12/04 Security  Hardware  Neuromorphic engineering  Computational modeling  Circuit faults  Resistance  Immune system  Adversarial attack  fault injection attack  neuromorphic computing system (NCS)  processing in memory  reliability  resistive memory
	Secured Data Transmission Over Insecure Networks-on-Chip by Modulating Inter-Packet Delays 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 11, 页码: 4313-4324 作者:  Xu, Jiaen;  Wang, Xiaohang;  Jiang, Yingtao;  Singh, Amit Kumar;  Gu, Chongyan;  Huang, Letian;  Yang, Mei;  Li, Shunbin 收藏  |  浏览/下载：13/0  |  提交时间：2023/07/12 Block coding  inter-packet delay  network-on-chip (NoC)  secure channel
	HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 10, 页码: 3400-3413 作者:  Liu, Cheng;  Chu, Cheng;  Xu, Dawen;  Wang, Ying;  Wang, Qianlong;  Li, Huawei;  Li, Xiaowei;  Cheng, Kwang-Ting 收藏  |  浏览/下载：25/0  |  提交时间：2022/12/07 Circuit faults  Computational modeling  Deep learning  Hardware  Redundancy  Neural networks  Computer architecture  Deep learning accelerator (DLA)  fault detection  fault tolerance  hybrid computing architecture (HyCA)
	An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 9, 页码: 2808-2820 作者:  Wang, Yongchen;  Wang, Ying;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：31/0  |  提交时间：2022/12/07 Streaming media  Neural networks  Image coding  Decoding  Metadata  Deep learning  Hardware  Neural network acceleration  specialized accelerator  video analysis
	Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 7, 页码: 2115-2127 作者:  He, Yintao;  Wang, Ying;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：27/0  |  提交时间：2022/12/07 Computer architecture  Microprocessors  Resistance  Power demand  Training  Biological neural networks  Optimization  Low power (LP)  neural networks  processing-in-memory  resistive random-access memory (RRAM)