中国科学院计算技术研究所机构知识库

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限定条件	出处：JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	Extracting Variable-Depth Logical Document Hierarchy from Long Documents: Method, Evaluation, and Application 期刊论文 JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2022, 卷号: 37, 期号: 3, 页码: 699-718 作者:  Cao, Rong-Yu;  Cao, Yi-Xuan;  Zhou, Gan-Bin;  Luo, Ping 收藏  |  浏览/下载：18/0  |  提交时间：2022/12/07 logical document hierarchy  long document  passage retrieval
	Physical Implementation of the Eight-Core Godson-3B Microprocessor 期刊论文 JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2011, 卷号: 26, 期号: 3, 页码: 520-527 作者:  Wang, Ru;  Fan, Bao-Xia;  Yang, Liang;  Gao, Yan-Ping;  Liu, Dong;  Xiao, Bin;  Wang, Jiang-Mei;  Zhang, Yi-Fu;  Wang, Hong;  Hu, Wei-Wu 收藏  |  浏览/下载：81/0  |  提交时间：2019/12/16 physical implementation  hierarchical design flow  GALS  clock mesh  low power
	Physical Design Methodology for Godson-2G Microprocessor 期刊论文 JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2010, 卷号: 25, 期号: 2, 页码: 225-231 作者:  Zhao, Ji-Ye;  Liu, Dong;  Huan, Dan-Dan;  Su, Meng-Hao;  Xiao, Bin;  Xu, Ying;  Shi, Feng;  Chen, Chen;  Wang, Song 收藏  |  浏览/下载：55/0  |  提交时间：2019/12/16 computer architecture  Godson-2G  physical design methodology  nanometer process
	Physical Implementation of the 1GHz Godson-3 Quad-Core Microprocessor 期刊论文 JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2010, 卷号: 25, 期号: 2, 页码: 192-199 作者:  Fan, Bao-Xia;  Yang, Liang;  Wang, Jiang-Mei;  Wang, Ru;  Xiao, Bin;  Xu, Ying;  Liu, Dong;  Zhao, Ji-Ye 收藏  |  浏览/下载：54/0  |  提交时间：2019/12/16 physical implementation  design methodology  on-chip variation (OCV)  low power  clock tree
	Implementing a 1GHz four-issue out-of-order execution microprocessor in a standard cell ASIC methodology 期刊论文 JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2007, 卷号: 22, 期号: 1, 页码: 1-14 作者:  Hu, Wei-Wu;  Zhao, Ji-Ye;  Zhong, Shi-Qiang;  Yang, Xu;  Guidetti, Elio;  Wu, Chris 收藏  |  浏览/下载：40/0  |  提交时间：2019/12/16 general-purpose processor  superscalar pipeline  out-of-order execution  non-blocking cache  physical design  synthesis flow  bit-sliced placement  crafted cell  performance evaluation