中国科学院计算技术研究所机构知识库

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限定条件	出处：IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS    作者：Li, Xiaowei    第一作者

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 5, 页码: 1504-1517 作者:  Mu, Jianan;  Ren, Yi;  Wang, Wen;  Hu, Yizhong;  Chen, Shuai;  Chang, Chip-Hong;  Fan, Junfeng;  Ye, Jing;  Cao, Yuan;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：9/0  |  提交时间：2023/12/04 Memory access pattern  number theoretic transform (NTT)  post-quantum cryptography (PQC)  scalable hardware design
	HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 10, 页码: 3400-3413 作者:  Liu, Cheng;  Chu, Cheng;  Xu, Dawen;  Wang, Ying;  Wang, Qianlong;  Li, Huawei;  Li, Xiaowei;  Cheng, Kwang-Ting 收藏  |  浏览/下载：26/0  |  提交时间：2022/12/07 Circuit faults  Computational modeling  Deep learning  Hardware  Redundancy  Neural networks  Computer architecture  Deep learning accelerator (DLA)  fault detection  fault tolerance  hybrid computing architecture (HyCA)
	Retention-Aware DRAM Assembly and Repair for Future FGR Memories 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2017, 卷号: 36, 期号: 5, 页码: 705-718 作者:  Wang, Ying;  Han, Yin-He;  Wang, Cheng;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：39/0  |  提交时间：2019/12/12 DDR  dynamic random-access memory (DRAM)  memory  refresh