Institute of Computing Technology, Chinese Academy IR
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| 当前检索式 | ((ALL：last-level cache (LLC))) |
| 限定条件 | ((出处：IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS) AND (作者：Wu, Bi) AND (资助项目：National Key Technology Program of China[2017ZX01032101])) |
| Cheng, Yuanqing 1 | Liu, Dijun 1 | Wang, Ying 1 |
| Wu, Bi 1 | Zhang, Beibei 1 | Zhao, Weisheng 1 |
