Tight Upper Bound for Accelerating Reconfiguration of VLSI Arrays

doi:10.1142/S0218126615500991

	Tight Upper Bound for Accelerating Reconfiguration of VLSI Arrays
	Wu, Jigang 1,2; Han, Xiaogang 3
	2015-08-01
发表期刊	JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
ISSN	0218-1266
卷号	24 期号:7 页码:10
摘要	Reconfiguring a very large scale integration (VLSI) array with faults is to construct a maximum logical sub-array (target array) without faults. A large target array implies a good harvest of the corresponding reconfiguration algorithm. Thus, a tight upper bound of the harvest can be directly used to evaluate the performance of the reconfiguration algorithm. This paper presents a new approach to calculate the upper bound of the harvest for the VLSI arrays with clustered faults. The latest upper bound is successfully reduced and the proposed technique to calculate the upper bound is bound into a reconfiguration algorithm cited in this paper. Simulation results show that the upper bound is reduced up to 20% on 256 x 256 array with clustered faults, and the corresponding reconfiguration process is significantly accelerated over 30%, without loss of harvest.
关键词	Reconfiguration VLSI array fault tolerance upper bound
DOI	10.1142/S0218126615500991
收录类别	SCI
语种	英语
资助项目	National Science and Technology Pillar Program of China[2015BAK19B03]
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:000356446200006
出版者	WORLD SCIENTIFIC PUBL CO PTE LTD
引用统计	被引频次：1[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/9648
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Wu, Jigang
作者单位	1.Guangdong Univ Technol, Sch Comp Sci & Technol, Guangzhou 510006, Guangdong, Peoples R China 2.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China 3.Nanyang Technol Univ, Sch Comp Engn, Singapore 639798, Singapore
推荐引用方式 GB/T 7714	Wu, Jigang,Han, Xiaogang. Tight Upper Bound for Accelerating Reconfiguration of VLSI Arrays[J]. JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS,2015,24(7):10.
APA	Wu, Jigang,&Han, Xiaogang.(2015).Tight Upper Bound for Accelerating Reconfiguration of VLSI Arrays.JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS,24(7),10.
MLA	Wu, Jigang,et al."Tight Upper Bound for Accelerating Reconfiguration of VLSI Arrays".JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 24.7(2015):10.