On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time

doi:10.1049/cje.2016.01.010

	On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time
	Wang Fei 1; Wang Da 2; Yang Haigang 2; Xie Xianghui 3; Fan Dongrui 1
	2016
发表期刊	CHINESE JOURNAL OF ELECTRONICS
ISSN	1022-4653
卷号	25 期号:1 页码:64-70
摘要	Statistics shows that over 95% of FPGA manufacturing test time is spent on loading test configuration bitstreams. Reducing the test time that spent on loading test configuration bitstreams could significantly reduce FPGA test time. A new approach which can significantly reduce the FPGA test time is presented. Experimental results show that the proposed technique can at least reduce the configuration loading time by 96%, while getting 100% test coverage with less than 1.2% hardware overhead.
关键词	FPGA test Test configuration bitstream Design-for-testability
DOI	10.1049/cje.2016.01.010
收录类别	SCI
语种	英语
资助项目	National Basic Research Program of China (973 Program)[2011CB302501] ; National High Technology Research and Development Program of China (863 Program)[2015AA01A301] ; National Science Foundation of China[61204047] ; National Science Foundation of China[61204045] ; National Science Foundation of China[61332009] ; Major Project of China[2013ZX0102-8001-001-001] ; Beijing Natural Science Foundation[4143060]
WOS研究方向	Engineering
WOS类目	Engineering, Electrical & Electronic
WOS记录号	WOS:000368322800010
出版者	TECHNOLOGY EXCHANGE LIMITED HONG KONG
引用统计	被引频次：1[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/8906
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Wang Fei
作者单位	1.Chinese Acad Sci, IE, Syst Programmable Chip Res Dept, Beijing 100190, Peoples R China 2.Chinese Acad Sci, ICT, State Key Lab Comp Architecture, Beijing 100190, Peoples R China 3.State Key Lab Math Engn & Adv Comp, Wuxi 214125, Peoples R China
推荐引用方式 GB/T 7714	Wang Fei,Wang Da,Yang Haigang,et al. On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time[J]. CHINESE JOURNAL OF ELECTRONICS,2016,25(1):64-70.
APA	Wang Fei,Wang Da,Yang Haigang,Xie Xianghui,&Fan Dongrui.(2016).On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time.CHINESE JOURNAL OF ELECTRONICS,25(1),64-70.
MLA	Wang Fei,et al."On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time".CHINESE JOURNAL OF ELECTRONICS 25.1(2016):64-70.