A Non-Stop Double Buffering Mechanism for Dataflow Architecture

doi:10.1007/s11390-017-1747-6

	A Non-Stop Double Buffering Mechanism for Dataflow Architecture
	Tan, Xu 1,2; Shen, Xiao-Wei 1,2; Ye, Xiao-Chun 1,3; Wang, Da 1; Fan, Dong-Rui 1,2; Zhang, Lunkai 4; Li, Wen-Ming 1; Zhang, Zhi-Min 1; Tang, Zhi-Min 1
	2018
发表期刊	JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY
ISSN	1000-9000
卷号	33 期号:1 页码:145-157
摘要	Double buffering is an effective mechanism to hide the latency of data transfers between on-chip and off-chip memory. However, in dataflow architecture, the swapping of two buffers during the execution of many tiles decreases the performance because of repetitive filling and draining of the dataflow accelerator. In this work, we propose a non-stop double buffering mechanism for dataflow architecture. The proposed non-stop mechanism assigns tiles to the processing element array without stopping the execution of processing elements through optimizing control logic in dataflow architecture. Moreover, we propose a work-flow program to cooperate with the non-stop double buffering mechanism. After optimizations both on control logic and on work-flow program, the filling and draining of the array needs to be done only once across the execution of all tiles belonging to the same dataflow graph. Experimental results show that the proposed double buffering mechanism for dataflow architecture achieves a 16.2% average efficiency improvement over that without the optimization.
关键词	non-stop double buffering dataflow architecture high-performance computing
DOI	10.1007/s11390-017-1747-6
收录类别	SCI
语种	英语
资助项目	National Key Research and Development Program of China[2016YFB0200501] ; National Natural Science Foundation of China[61332009] ; National Natural Science Foundation of China[61521092] ; Open Project Program of State Key Laboratory of Mathematical Engineering and Advanced Computing[2016A04] ; Beijing Municipal Science and Technology Commission[Z15010101009]
WOS研究方向	Computer Science
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Software Engineering
WOS记录号	WOS:000423587100009
出版者	SCIENCE PRESS
引用统计	被引频次：6[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/6189
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Fan, Dong-Rui
作者单位	1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China 2.Univ Chinese Acad Sci, Sch Comp & Control Engn, Beijing 100049, Peoples R China 3.State Key Lab Math Engn & Adv Comp, Wuxi 214125, Peoples R China 4.Univ Chicago, Dept Comp Sci, Chicago, IL 60637 USA
推荐引用方式 GB/T 7714	Tan, Xu,Shen, Xiao-Wei,Ye, Xiao-Chun,et al. A Non-Stop Double Buffering Mechanism for Dataflow Architecture[J]. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,2018,33(1):145-157.
APA	Tan, Xu.,Shen, Xiao-Wei.,Ye, Xiao-Chun.,Wang, Da.,Fan, Dong-Rui.,...&Tang, Zhi-Min.(2018).A Non-Stop Double Buffering Mechanism for Dataflow Architecture.JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,33(1),145-157.
MLA	Tan, Xu,et al."A Non-Stop Double Buffering Mechanism for Dataflow Architecture".JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 33.1(2018):145-157.