A Pipelining Loop Optimization Method for Dataflow Architecture

doi:10.1007/s11390-017-1748-5

	A Pipelining Loop Optimization Method for Dataflow Architecture
	Tan, Xu 1,2; Ye, Xiao-Chun 1,3; Shen, Xiao-Wei 1,2; Xu, Yuan-Chao 1,4; Wang, Da 1; Zhang, Lunkai 5; Li, Wen-Ming 1; Fan, Dong-Rui 1,2; Tang, Zhi-Min 1
	2018
发表期刊	JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY
ISSN	1000-9000
卷号	33 期号:1 页码:116-130
摘要	With the coming of exascale supercomputing era, power efficiency has become the most important obstacle to build an exascale system. Dataflow architecture has native advantage in achieving high power efficiency for scientific applications. However, the state-of-the-art dataflow architectures fail to exploit high parallelism for loop processing. To address this issue, we propose a pipelining loop optimization method (PLO), which makes iterations in loops flow in the processing element (PE) array of dataflow accelerator. This method consists of two techniques, architecture-assisted hardware iteration and instruction-assisted software iteration. In hardware iteration execution model, an on-chip loop controller is designed to generate loop indexes, reducing the complexity of computing kernel and laying a good foundation for pipelining execution. In software iteration execution model, additional loop instructions are presented to solve the iteration dependency problem. Via these two techniques, the average number of instructions ready to execute per cycle is increased to keep floating-point unit busy. Simulation results show that our proposed method outperforms static and dynamic loop execution model in floating-point efficiency by 2.45x and 1.1x on average, respectively, while the hardware cost of these two techniques is acceptable.
关键词	dataflow model control-flow model loop optimization exascale computing scientific application
DOI	10.1007/s11390-017-1748-5
收录类别	SCI
语种	英语
资助项目	National Key Research and Development Program of China[2016YFB0200501] ; National Natural Science Foundation of China[61332009] ; National Natural Science Foundation of China[61521092] ; Open Project Program of State Key Laboratory of Mathematical Engineering and Advanced Computing[2016A04] ; Beijing Municipal Science and Technology Commission[Z15010101009] ; Open Project Program of State Key Laboratory of Computer Architecture[CARCH201503] ; China Scholarship Council ; Beijing Advanced Innovation Center for Imaging Technology
WOS研究方向	Computer Science
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Software Engineering
WOS记录号	WOS:000423587100007
出版者	SCIENCE PRESS
引用统计	被引频次：6[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/5608
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Xu, Yuan-Chao
作者单位	1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China 2.Univ Chinese Acad Sci, Sch Comp & Control Engn, Beijing 100049, Peoples R China 3.State Key Lab Math Engn & Adv Comp, Wuxi 214125, Peoples R China 4.Capital Normal Univ, Coll Informat Engn, Beijing 100048, Peoples R China 5.Univ Chicago, Dept Comp Sci, Chicago, IL 60637 USA
推荐引用方式 GB/T 7714	Tan, Xu,Ye, Xiao-Chun,Shen, Xiao-Wei,et al. A Pipelining Loop Optimization Method for Dataflow Architecture[J]. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,2018,33(1):116-130.
APA	Tan, Xu.,Ye, Xiao-Chun.,Shen, Xiao-Wei.,Xu, Yuan-Chao.,Wang, Da.,...&Tang, Zhi-Min.(2018).A Pipelining Loop Optimization Method for Dataflow Architecture.JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,33(1),116-130.
MLA	Tan, Xu,et al."A Pipelining Loop Optimization Method for Dataflow Architecture".JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 33.1(2018):116-130.