A VLSI-oriented parallel FFT algorithm

	A VLSI-oriented parallel FFT algorithm
	Ma, YT
	1996-02-01
发表期刊	IEEE TRANSACTIONS ON SIGNAL PROCESSING
ISSN	1053-587X
卷号	44 期号:2 页码:445-448
摘要	Usually, parallel pipelined PFT processors are used to compute long FFT's due to high processing rate and easy implementation. The efficient VLSI implementation of each FFT processor at the pipelines is a critical problem to be considered. We propose a new parallel FFT algorithm that removes the complex multiplier between the two pipeline stages. The new algorithm also simplifies the address generation of twiddle factors and reduces the number of twiddle factors to a minimum. With the new algorithm, each FFT processor at the pipelines can be integrated easily onto a single chip.
收录类别	SCI
语种	英语
WOS研究方向	Engineering
WOS类目	Engineering, Electrical & Electronic
WOS记录号	WOS:A1996UB15800031
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：9[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/5446
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Ma, YT
作者单位	CHINESE ACAD SCI,INST COMP TECHNOL,CTR HIGH PERFORMANCE COMP,BEIJING,PEOPLES R CHINA
推荐引用方式 GB/T 7714	Ma, YT. A VLSI-oriented parallel FFT algorithm[J]. IEEE TRANSACTIONS ON SIGNAL PROCESSING,1996,44(2):445-448.
APA	Ma, YT.(1996).A VLSI-oriented parallel FFT algorithm.IEEE TRANSACTIONS ON SIGNAL PROCESSING,44(2),445-448.
MLA	Ma, YT."A VLSI-oriented parallel FFT algorithm".IEEE TRANSACTIONS ON SIGNAL PROCESSING 44.2(1996):445-448.