HARLD: A RISC-V Based Tightly Coupled Heterogeneous Computing Architecture for Low-Density Parity Check Decoding

doi:10.1007/s11390-025-5052-5

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	HARLD: A RISC-V Based Tightly Coupled Heterogeneous Computing Architecture for Low-Density Parity Check Decoding
	Wang, Bing 1; Ma, Zi-Rui 2,3; Wu, Hai-Bin 2; Zhang, Fu-Lin 2,3; Yue Wang, Yue Wang 2,3; Fan, Zhi-Hua 2,3; Li, Wen-Ming 2,3; Ye, Xiao-Chun 2,3; Fan, Dong-Rui 2,3
	2026-01-21
发表期刊	JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY
ISSN	1000-9000
页码	17
摘要	Low-density parity check (LDPC) decoding is an efficient error correction method in communication systems, especially in 5G networks, which require high performance and low latency; while common generalpurpose architectures cannot meet the requirements. There has been some research on accelerating LDPC decoding, but the current methods still suffer from limitations in performance, flexibility, and communication cost. In this paper, we propose HARLD (Heterogeneous Architecture of RISC-V for LDPC Decoding), a tightly coupled heterogeneous computing architecture based on extended RISC-V for LDPC decoding, consisting of a CPU and a processing array. Compared with a loosely coupled System-on-Chip (SoC)-bus baseline, the tightly coupled design improves throughput by up to 32.4% and reduces average latency by up to 24.7% across evaluated configurations, while also enhancing resource and energy efficiency: processing element utilization up to 93.5%, instruction RAM utilization increased by up to 4.8x, and energy efficiency improved by up to 24.8%. At the system level, area and power are reduced by 17.6% and 10.2%, respectively, versus the loosely coupled design.
关键词	tightly coupled heterogeneous computing architecture low-density parity check (LDPC) decoding RISC-V extension
DOI	10.1007/s11390-025-5052-5
收录类别	SCI
语种	英语
WOS研究方向	Computer Science
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Software Engineering
WOS记录号	WOS:001666429900001
出版者	SPRINGER SINGAPORE PTE LTD
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/42882
专题	中国科学院计算技术研究所
通讯作者	Wu, Hai-Bin
作者单位	1.China Mobile Res Inst, Beijing 100053, Peoples R China 2.Chinese Acad Sci, Inst Comp Technol, State Key Lab Processors, Beijing 100190, Peoples R China 3.Univ Chinese Acad Sci, Beijing 100049, Peoples R China
推荐引用方式 GB/T 7714	Wang, Bing,Ma, Zi-Rui,Wu, Hai-Bin,et al. HARLD: A RISC-V Based Tightly Coupled Heterogeneous Computing Architecture for Low-Density Parity Check Decoding[J]. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,2026:17.
APA	Wang, Bing.,Ma, Zi-Rui.,Wu, Hai-Bin.,Zhang, Fu-Lin.,Yue Wang, Yue Wang.,...&Fan, Dong-Rui.(2026).HARLD: A RISC-V Based Tightly Coupled Heterogeneous Computing Architecture for Low-Density Parity Check Decoding.JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,17.
MLA	Wang, Bing,et al."HARLD: A RISC-V Based Tightly Coupled Heterogeneous Computing Architecture for Low-Density Parity Check Decoding".JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY (2026):17.