A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition

doi:10.1016/j.vlsi.2019.02.008

	A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition
	Wei, Xing 1,3,4; Yang, Haigang 1,3; Li, Wei 3,5; Huang, Zhihong 1,3; Yin, Tao 1,3; Yu, Le 2
	2019-05-01
发表期刊	INTEGRATION-THE VLSI JOURNAL
ISSN	0167-9260
卷号	66 页码:164-172
摘要	This paper presents a high throughput size-configurable floating point (FP) Fast Fourier Transform (FFT) processor, having implemented the 8-parallel multi-path delay feedback (MDF) functions suitable for applications in the real-time radar imaging system. With regard to floating-point FFT design, to acquire a high throughput with restricted area and power consumptions poses as a greater challenge due to some higher degrees of complexity involved in realizing of FP operations than those fixed-point counterparts. To address the related issues, a novel mixed-radix FFT algorithm featuring the single-sided binary-tree decomposition strategy is proposed aiming at effectively containing the complexity of multiplications for any 2(k)-point FFT. To this aid, the parallel-processing twiddle factor generator and the dual addition-and-rounding fused FP arithmetic units are optimized to meet the high accuracy demand in computation and the low power budget in implementation. The proposed FP FFT processor has been designed in silicon based on SMIC's 28 nm CMOS technology with the active area of 1.39 mm(2). The prototype design delivers a throughput of 4 GSample/s at 500 MHz, at a peak power consumption of 84.2 mW. Thus, the proposed design approach achieves a significant improvement in power efficiency approximately by 14 times on average over some other FP FFT processors previously reported.
关键词	Floating-point Fast fourier transform (FFT) Mixed-radix Multi-path delay feedback (MDF) Binary-tree decomposition Twiddle factor Fused FP arithmetic unit
DOI	10.1016/j.vlsi.2019.02.008
收录类别	SCI
语种	英语
资助项目	National Natural Science Foundation of China[61876172] ; National Natural Science Foundation of China[61704173] ; Major Program of Beijing Science and Technology[Z171100000117019] ; Beijing Key Laboratory of Big Data Technology for Food Safety, Beijing Technology and Business University[BKBD-2017KF05]
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:000469905300017
出版者	ELSEVIER SCIENCE BV
引用统计	被引频次：1[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/4216
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Yang, Haigang; Yu, Le
作者单位	1.Chinese Acad Sci, Inst Elect, Beijing 100190, Peoples R China 2.Beijing Technol & Business Univ, Beijing Key Lab Big Data Technol Food Safety, Beijing 100048, Peoples R China 3.Univ Chinese Acad Sci, Beijing 100049, Peoples R China 4.China Acad Elect & Informat Technol, Beijing 100041, Peoples R China 5.Chinese Acad Sci, Inst Comp Technol, Beijing 100190, Peoples R China
推荐引用方式 GB/T 7714	Wei, Xing,Yang, Haigang,Li, Wei,et al. A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition[J]. INTEGRATION-THE VLSI JOURNAL,2019,66:164-172.
APA	Wei, Xing,Yang, Haigang,Li, Wei,Huang, Zhihong,Yin, Tao,&Yu, Le.(2019).A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition.INTEGRATION-THE VLSI JOURNAL,66,164-172.
MLA	Wei, Xing,et al."A reconfigurable 4-GS/s power-efficient floating-point FFT processor design and implementation based on single-sided binary-tree decomposition".INTEGRATION-THE VLSI JOURNAL 66(2019):164-172.