PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators

doi:10.1109/TCAD.2024.3496847

	PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators
	Sun, Xiaotian 1,2; Wang, Xinyu 1,2; Li, Wanqian 1,2; Han, Yinhe 1,2; Chen, Xiaoming 1,2
	2025-05-01
发表期刊	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
ISSN	0278-0070
卷号	44 期号:5 页码:1745-1759
摘要	In the past decade, various processing-in-memory (PIM) accelerators based on various devices, micro-architectures, and interfaces have been proposed to accelerate deep neural networks (DNNs). How to deploy DNNs onto PIM-based accelerators is the key to explore PIM's high performance and energy efficiency. The scale of DNN models, the diversity of PIM accelerators, and the complexity of deployment are far beyond the human deployment capability. Hence, an automatic deployment methodology is indispensable. In this work, we propose PIMCOMP, an end-to-end DNN compiler tailored for PIM accelerators, achieving efficient deployment of DNN models on PIM hardware. PIMCOMP can adapt to various PIM architectures by using an abstract configurable PIM accelerator template with a set of pseudo instructions, which is a high-level abstraction of the hardware's fundamental functionalities. Through a generic multilevel optimization framework, PIMCOMP realizes an end-to-end conversion from a high-level DNN description to pseudo instructions, which can be further converted to specific hardware intrinsics/primitives. The compilation addresses two critical issues in PIM-accelerated inference from a system perspective: 1) resource utilization and 2) dataflow scheduling. PIMCOMP adopts a flexible unfolding format to reshape and partition convolutional layers, adopts a weight-layout guided computation-storage-mapping approach to enhance resource utilization, and balances the system's computation, memory access, and communication characteristics. For dataflow scheduling, we design two scheduling algorithms with different interlayer pipeline granularities to support varying application scenarios while ensuring high-computational parallelism. Experiments demonstrate that PIMCOMP improves throughput, latency, and energy efficiency across various architectures. PIMCOMP is open-sourced at https://github.com/sunxt99/PIMCOMP-NN.
关键词	Hardware Optimization Artificial neural networks Pipelines Parallel processing Biological system modeling Resource management Adaptation models Scheduling Memory management Deep neural network (DNN) end-to-end compiler processing-in-memory (PIM) accelerator system-level optimization
DOI	10.1109/TCAD.2024.3496847
收录类别	SCI
语种	英语
资助项目	Strategic Priority Research Program of CAS[XDB44000000] ; National Natural Science Foundation of China[62122076] ; National Natural Science Foundation of China[62025404] ; National Natural Science Foundation of China[62488101] ; Key Research Program of Frontier Sciences, CAS[ZDBS-LY-JSC012] ; Youth Innovation Promotion Association CAS
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Interdisciplinary Applications ; Engineering, Electrical & Electronic
WOS记录号	WOS:001473569900031
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/40623
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Chen, Xiaoming
作者单位	1.Chinese Acad Sci, Inst Comp Technol, Beijing 100190, Peoples R China 2.Univ Chinese Acad Sci, Beijing 100190, Peoples R China
推荐引用方式 GB/T 7714	Sun, Xiaotian,Wang, Xinyu,Li, Wanqian,et al. PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2025,44(5):1745-1759.
APA	Sun, Xiaotian,Wang, Xinyu,Li, Wanqian,Han, Yinhe,&Chen, Xiaoming.(2025).PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,44(5),1745-1759.
MLA	Sun, Xiaotian,et al."PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 44.5(2025):1745-1759.