An Instruction Inflation Analyzing Framework for Dynamic Binary Translators

doi:10.1145/3640813

	An Instruction Inflation Analyzing Framework for Dynamic Binary Translators
	Xie, Benyi 1,2; Yan, Yue 1,2; Yan, Chenghao 1,2; Tao, Sicheng 3; Zhang, Zhuangzhuang 3; Li, Xinyu 1,2; Lan, Yanzhi 1,2; Wu, Xiang 1,2; Liu, Tianyi 4; Zhang, Tingting 5,6; Zhang, Fuxin 1,2
	2024-06-01
发表期刊	ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION
ISSN	1544-3566
卷号	21 期号:2 页码:25
摘要	Dynamic binary translators (DBTs) are widely used to migrate applications between different instruction set architectures (ISAs). Despite extensive research to improve DBT performance, noticeable overhead remains, preventing near-native performance, especially when translating from complex instruction set computer (CISC) to reduced instruction set computer (RISC). For computational workloads, the main overhead stems from translated code quality. Experimental data show that state-of-the-art DBT products have dynamic code inflation of at least 1.46. This indicates that on average, more than 1.46 host instructions are needed to emulate one guest instruction. Worse, inflation closely correlates with translated code quality. However, the detailed sources of instruction inflation remain unclear. To understand the sources of inflation, we present Deflater, an instruction inflation analysis framework comprising a mathematical model, a collection of black-box unit tests called BenchMIAOes, and a trace-based simulator called InflatSim. The mathematical model calculates overall inflation based on the inflation of individual instructions and translation block optimizations. BenchMIAOes extract model parameters from DBTs without accessing DBT source code. InflatSim implements the model and uses the extracted parameters from BenchMIAOes to simulate a given DBT's behavior. Deflater is a valuable tool to guide DBT analysis and improvement. Using Deflater, we simulated inflation for three state-of-the-art CISC-to-RISC DBTs: ExaGear, Rosetta2, and LATX, with inflation errors of 5.63%, 5.15%, and 3.44%, respectively for SPEC CPU 2017, gaining insights into these commercial DBTs. Deflater also efficiently models inflation for the open source DBT QEMU and suggests optimizations that can substantially reduce inflation. Implementing the suggested optimizations confirms Deflater's effective guidance, with 4.65% inflation error, and gains 5.47x performance improvement.
关键词	Dynamic binary translation translation inflation overhead analysis
DOI	10.1145/3640813
收录类别	SCI
语种	英语
资助项目	National Key Research and Development Program of China[2022YFB3105104]
WOS研究方向	Computer Science
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Theory & Methods
WOS记录号	WOS:001242588100008
出版者	ASSOC COMPUTING MACHINERY
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/39893
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Xie, Benyi
作者单位	1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Processors, 6 Kexueyuan Nanlu, Beijing 100190, Peoples R China 2.Univ Chinese Acad Sci, 1 Yanqihu East Rd, Beijing, Peoples R China 3.Univ Sci & Technol China, 96 JinZhai Rd, Hefei 230026, Anhui, Peoples R China 4.Univ Texas San Antonio, 1 UTSA Circle, San Antonio, TX 78249 USA 5.Loongson Technol Co Ltd, ICT Loongson Pk,Daoxianghu Rd, Beijing 100095, Peoples R China 6.Chinese Acad Sci, Inst Comp Technol, 6 Kexueyuan Nanlu, Beijing 100190, Peoples R China
推荐引用方式 GB/T 7714	Xie, Benyi,Yan, Yue,Yan, Chenghao,et al. An Instruction Inflation Analyzing Framework for Dynamic Binary Translators[J]. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION,2024,21(2):25.
APA	Xie, Benyi.,Yan, Yue.,Yan, Chenghao.,Tao, Sicheng.,Zhang, Zhuangzhuang.,...&Zhang, Fuxin.(2024).An Instruction Inflation Analyzing Framework for Dynamic Binary Translators.ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION,21(2),25.
MLA	Xie, Benyi,et al."An Instruction Inflation Analyzing Framework for Dynamic Binary Translators".ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 21.2(2024):25.