FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer

doi:10.1109/TCSI.2024.3419579

	FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer
	Jiao, Bo 1; Xu, Lei 1; Yu, Xinyu 1; Yang, Haitao 1; Zhu, Haozhe 1; Wang, Yu 2; Zhu, Jundong ; Wen, Dexin ; Wang, Lingli 1; Tao, Jun 1; Chen, Chixiao 1; Han, Yinhe 3; Liu, Qi 1; Sun, Ninghui ; Liu, Ming 1
	2024-07-04
发表期刊	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
ISSN	1549-8328
页码	13
摘要	Silicon interposer re-usage is drawing attention for cost-effective multi-chiplet integrated systems. To address the communication awareness of inter/off-chiplet interconnect, the paper proposes a field-programmable interconnect fabric and develops its corresponding automatic physical integration tool. The tile-based fabric consists of turnout, cross-over boxes and parallel tracks. It features micro-bump-wise connecting flexibility and hardware efficiency. The automation flow performs chiplet location optimization and efficient bump-to-bump routing, supporting multi-lane bus interconnect and miscellaneous external ports. The methodology is validated by 9 different integration scenarios, where the routability is guaranteed when the local resource utilization ratio approaches 94.5%. The data's maximum interconnect latency is 2.2 ns and the energy consumption is 1.18 pJ/bit at a bitrate of 1 Gbps. The latency consumes 16.5x similar to 53.4x fewer clock cycles than the state-of-the-art network-on-package-based reusable interposer architectures.
关键词	Chiplet integration silicon interposer placement routing communication-aware
DOI	10.1109/TCSI.2024.3419579
收录类别	SCI
语种	英语
资助项目	National Key Research and Development Program of China[2023YFB4404402] ; National Natural Science Foundation of China (NSFC)[62322404] ; National Natural Science Foundation of China (NSFC)[61732020] ; National Natural Science Foundation of China (NSFC)[92373001]
WOS研究方向	Engineering
WOS类目	Engineering, Electrical & Electronic
WOS记录号	WOS:001263407600001
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/39849
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Tao, Jun; Chen, Chixiao
作者单位	1.Fudan Univ, Frontier Inst Chip & Syst, State Key Lab Integrated Chips & Syst, Shanghai 200433, Peoples R China 2.Kiwimoore Shanghai Semicond Co Ltd, Shanghai 200433, Peoples R China 3.Chinese Acad Sci, Inst Comp Technol, Beijing 100190, Peoples R China
推荐引用方式 GB/T 7714	Jiao, Bo,Xu, Lei,Yu, Xinyu,et al. FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,2024:13.
APA	Jiao, Bo.,Xu, Lei.,Yu, Xinyu.,Yang, Haitao.,Zhu, Haozhe.,...&Liu, Ming.(2024).FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,13.
MLA	Jiao, Bo,et al."FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2024):13.