Institute of Computing Technology, Chinese Academy IR
A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks | |
He, Yintao1,2; Li, Bing3; Wang, Ying4; Liu, Cheng1,2; Li, Huawei5; Li, Xiaowei1,2,6,7 | |
2024-09-01 | |
发表期刊 | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS |
ISSN | 0278-0070 |
卷号 | 43期号:9页码:2635-2646 |
摘要 | ReRAM-based computing-in-memory (CiM) architecture has been considered a promising solution to high-efficiency neural network accelerator, by conducting in-situ matrix multiplications and eliminating the movement of neural parameters from off-chip memory to computing units. However, we observed specific features of graph convolutional network (GCN) tasks pose design challenges to implement a high-efficiency ReRAM GCN accelerator. The ultralarge input feature data in some GCN tasks incur massive data movements, the extremely sparse adjacency matrix and input feature data involve the valid computation, and the super-large adjacency matrix that exceeds available ReRAM capacity causes frequent expensive write operations. To address the above challenges, we propose TARe, a task-adaptive CiM architecture, which consists of a hybrid in-situ computing mode to support the input feature in crossbar computing, a compact mapping scheme for efficient sparse matrix computing, and a write-free mapping to eliminate write activities in the computations with the super-large adjacency matrix. Additionally, TARe is facilitated with a task adaptive selection algorithm to generate optimized design schemes for graph neural network (GNN) tasks that have various operand sizes and data sparsity. We evaluate TARe on 11 diverse GNN tasks and compare it with different design counterparts, and the results show that achieves 168.06 $\times $ speedup and 10.95 $\times $ energy consumption reduction on average over the baseline in common GCN workloads. |
关键词 | Task analysis Sparse matrices Convolution Convolutional neural networks Design automation Neural networks Integrated circuits Graph convolutional network hardware acceleration processing-in-memory |
DOI | 10.1109/TCAD.2024.3375251 |
收录类别 | SCI |
语种 | 英语 |
资助项目 | National Natural Science Foundation of China (NSFC)[62090024] ; National Natural Science Foundation of China (NSFC)[62222411] ; National Natural Science Foundation of China (NSFC)[92373206] ; National Natural Science Foundation of China (NSFC)[62204164] |
WOS研究方向 | Computer Science ; Engineering |
WOS类目 | Computer Science, Hardware & Architecture ; Computer Science, Interdisciplinary Applications ; Engineering, Electrical & Electronic |
WOS记录号 | WOS:001297718600006 |
出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
引用统计 | |
文献类型 | 期刊论文 |
条目标识符 | http://119.78.100.204/handle/2XEOYT63/39610 |
专题 | 中国科学院计算技术研究所期刊论文_英文 |
通讯作者 | Li, Bing; Li, Huawei |
作者单位 | 1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Processors, Beijing 100190, Peoples R China 2.Univ Chinese Acad Sci, Dept Comp Sci, Beijing 100190, Peoples R China 3.Capital Normal Univ, Acad Multidisciplinary Studies, Beijing 100037, Peoples R China 4.Chinese Acad Sci, Inst Comp Technol, CICS, Beijing 100190, Peoples R China 5.Chinese Acad Sci, Inst Comp Technol, State Key Lab Processors, Beijing 100190, Peoples R China 6.Univ Chinese Acad Sci, Beijing 100190, Peoples R China 7.Peng Cheng Lab, Shenzhen 518066, Peoples R China |
推荐引用方式 GB/T 7714 | He, Yintao,Li, Bing,Wang, Ying,et al. A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2024,43(9):2635-2646. |
APA | He, Yintao,Li, Bing,Wang, Ying,Liu, Cheng,Li, Huawei,&Li, Xiaowei.(2024).A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,43(9),2635-2646. |
MLA | He, Yintao,et al."A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 43.9(2024):2635-2646. |
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