Institute of Computing Technology, Chinese Academy IR
MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures | |
Zhu, Zhenhua1; Sun, Hanbo1; Xie, Tongxin1; Zhu, Yu1; Dai, Guohao2; Xia, Lixue3; Niu, Dimin4; Chen, Xiaoming5; Hu, Xiaobo Sharon6; Cao, Yu7; Xie, Yuan4; Yang, Huazhong1; Wang, Yu1 | |
2023-11-01 | |
发表期刊 | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS |
ISSN | 0278-0070 |
卷号 | 42期号:11页码:4112-4125 |
摘要 | In the age of artificial intelligence (AI), the huge data movements between memory and computing units become the bottleneck of von Neumann architectures, i.e., the "memory wall" problem. In order to tackle this challenge, processing-in-memory (PIM) architectures are proposed, which perform in-situ computations in memory and give alternative solutions to boost the computing energy efficiency and performance. Because of the large-scale neural network (NN) algorithm models and the huge hardware design space, various factors affect computing accuracy and performance, bringing the need for efficient PIM modeling and evaluation tools. In this work, we propose a behavior-level modeling tool, MNSIM 2.0, to model the performance of PIM architectures efficiently. At the hardware level, MNSIM 2.0 provides a hierarchical PIM modeling structure with flexible architecture configurability and components extensibility. Moreover, the first unified PIM memory array model is proposed for describing both digital and analog PIM. At the algorithm level, MNSIM 2.0 supports the PIM-based NN computing accuracy simulation considering various architecture and device parameters. A PIM-oriented NN model training and quantization flow is also integrated to improve the performance gain brought by PIM. At the scheduling level, MNSIM 2.0 adopts a universal scheduling description compatible with different scheduling strategies. Validation using fabricated PIM macros shows the relative modeling error rate of MNSIM 2.0 is 3.8%-5.5%. Case studies show that MNSIM 2.0 enables PIM design space explorations, influences analysis of device parameters, and architecture design insight discoveries. |
关键词 | Computational modeling Computer architecture Integrated circuit modeling Scheduling Hardware Memristors Convolutional neural networks Hardware modeling tool processing-in-memory (PIM) software-hardware co-optimization |
DOI | 10.1109/TCAD.2023.3251696 |
收录类别 | SCI |
语种 | 英语 |
资助项目 | Beijing Innovation Center for Future Chips ; Tsinghua-Meituan Joint Institute for Digital Life |
WOS研究方向 | Computer Science ; Engineering |
WOS类目 | Computer Science, Hardware & Architecture ; Computer Science, Interdisciplinary Applications ; Engineering, Electrical & Electronic |
WOS记录号 | WOS:001098114300048 |
出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
引用统计 | |
文献类型 | 期刊论文 |
条目标识符 | http://119.78.100.204/handle/2XEOYT63/38088 |
专题 | 中国科学院计算技术研究所期刊论文_英文 |
通讯作者 | Wang, Yu |
作者单位 | 1.Tsinghua Univ, Dept Elect Engn, Beijing 100084, Peoples R China 2.Shanghai Jiao Tong Univ, Qing Yuan Res Inst, Shanghai 200030, Peoples R China 3.Alibaba Grp, Dept Cloud Intelligence, Beijing 100022, Peoples R China 4.Alibaba DAMO Acad, Comp Technol Lab, Hangzhou 311121, Peoples R China 5.Chinese Acad Sci, Inst Comp Technol, Beijing 100045, Peoples R China 6.Univ Notre Dame, Dept Comp Sci & Engn, Notre Dame, IN 46556 USA 7.Arizona State Univ, Sch Elect Comp & Energy Engn, Tempe, AZ 85281 USA |
推荐引用方式 GB/T 7714 | Zhu, Zhenhua,Sun, Hanbo,Xie, Tongxin,et al. MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2023,42(11):4112-4125. |
APA | Zhu, Zhenhua.,Sun, Hanbo.,Xie, Tongxin.,Zhu, Yu.,Dai, Guohao.,...&Wang, Yu.(2023).MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,42(11),4112-4125. |
MLA | Zhu, Zhenhua,et al."MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 42.11(2023):4112-4125. |
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