Functional Verification for Agile Processor Development: A Case for Workflow Integration

doi:10.1007/s11390-023-3285-8

	Functional Verification for Agile Processor Development: A Case for Workflow Integration
	Xu, Yi-Nan 1,2; Yu, Zi-Hao 1; Wang, Kai-Fan 1,2; Wang, Hua-Qiang 1,2; Lin, Jia-Wei 1,2; Jin, Yue 1,2; Zhang, Lin-Juan 1,2; Zhang, Zi-Fei 1,2; Tang, Dan 1,3; Wang, Sa 1; Shi, Kan 1; Sun, Ning-Hui 1,2; Bao, Yun-Gang 1,2
	2023-07-01
发表期刊	JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY
ISSN	1000-9000
卷号	38 期号:4 页码:737-753
摘要	Agile hardware development methodology has been widely adopted over the past decade. Despite the research progress, the industry still doubts its applicability, especially for the functional verification of complicated processor chips. Functional verification commonly employs a simulation-based method of co-simulating the design under test with a reference model and checking the consistency of their outcomes given the same input stimuli. We observe limited collaboration and information exchange through the design and verification processes, dramatically leading to inefficiencies when applying the conventional functional verification workflow to agile development. In this paper, we propose workflow integration with collaborative task delegation and dynamic information exchange as the design principles to effectively address the challenges on functional verification under the agile development model. Based on workflow integration, we enhance the functional verification workflows with a series of novel methodologies and toolchains. The diff-rule based agile verification methodology (DRAV) reduces the overhead of building reference models with runtime execution information from designs under test. We present the RISC-V implementation for DRAV, DiffTest, which adopts information probes to extract internal design behaviors for co-simulation and debugging. It further integrates two plugins, namely XFUZZ for effective test generation guided by design coverage metrics and LightSSS for efficient fault analysis triggered by co-simulation mismatches. We present the integrated workflows for agile hardware development and demonstrate their effectiveness in designing and verifying RISC-V processors with 33 functional bugs found in NutShell. We also illustrate the efficiency of the proposed toolchains with a case study on a functional bug in the L2 cache of XiangShan.
关键词	functional verification agile development open-source hardware workflow integration
DOI	10.1007/s11390-023-3285-8
收录类别	SCI
语种	英语
资助项目	Strategic Priority Research Program of Chinese Academy of Sciences (CAS)[XDC05030200] ; National Key Research and Development Program of China[2022YFB4500403] ; National Natural Science Foundation of China[62090022] ; National Natural Science Foundation of China[62172388] ; Youth Innovation Promotion Association of the Chinese Academy of Sciences[2020105] ; Institute of Computing Technology, Chinese Academy of Sciences[E261100]
WOS研究方向	Computer Science
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Software Engineering
WOS记录号	WOS:001102032000002
出版者	SPRINGER SINGAPORE PTE LTD
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/38074
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Bao, Yun-Gang
作者单位	1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Processors, Beijing 100190, Peoples R China 2.Univ Chinese Acad Sci, Beijing 100049, Peoples R China 3.Beijing Inst Open Source Chip, Beijing 100080, Peoples R China
推荐引用方式 GB/T 7714	Xu, Yi-Nan,Yu, Zi-Hao,Wang, Kai-Fan,et al. Functional Verification for Agile Processor Development: A Case for Workflow Integration[J]. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,2023,38(4):737-753.
APA	Xu, Yi-Nan.,Yu, Zi-Hao.,Wang, Kai-Fan.,Wang, Hua-Qiang.,Lin, Jia-Wei.,...&Bao, Yun-Gang.(2023).Functional Verification for Agile Processor Development: A Case for Workflow Integration.JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,38(4),737-753.
MLA	Xu, Yi-Nan,et al."Functional Verification for Agile Processor Development: A Case for Workflow Integration".JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 38.4(2023):737-753.