Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation

doi:10.1109/TCAD.2022.3205552

	Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation
	Mu, Jianan 1,2,3; Ren, Yi 2,4; Wang, Wen 5; Hu, Yizhong 6; Chen, Shuai 7; Chang, Chip-Hong 8; Fan, Junfeng 6; Ye, Jing 1,3; Cao, Yuan 9; Li, Huawei 1,2,3; Li, Xiaowei 1,2,3
	2023-05-01
发表期刊	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
ISSN	0278-0070
卷号	42 期号:5 页码:1504-1517
摘要	Number theoretic transform (NTT) is useful for the acceleration of polynomial multiplication, which is the main performance bottleneck in the next-generation cryptographic schemes. Different NTT-based cryptographic algorithms have different security settings. The diverse application scenarios introduce different cost-performance tradeoffs and hardware constraints. Motivated by the emerging demand for more versatile NTT hardware accelerators, we propose a new design methodology that can generate area-efficient and high-performance NTT accelerators for any length and modulus of NTT polynomials and single processing element (PE) or PE array with a varying number of layers. The proposed NTT accelerator architecture pivots on a conflict-free memory access pattern for adaptation to different combinations of security and PE array configuration parameters. The proposed memory access pattern is formally proved to be conflict-free for any parametric configurations. The criterion for read-after-write conflict without pipeline stall is also established. Our proposed design methodology can produce NTT accelerators with single PE or multilayer PE array for different polynomial size and modulus, with hardware area and computational efficiency comparable to accelerators customized for a fixed set of parameters. Our proposed methodology produces parameterized accelerator with higher scalability than the existing parameterized accelerator design. On average, the accelerators generated by our proposed method are 71.4% more area-time efficient. Up to 30.7% area-time reduction over the most area-time efficient state-of-the-art scalable NTT accelerator can be achieved for the same security parameters.
关键词	Memory access pattern number theoretic transform (NTT) post-quantum cryptography (PQC) scalable hardware design
DOI	10.1109/TCAD.2022.3205552
收录类别	SCI
语种	英语
资助项目	National Key Research and Development Program of China[2020YFB1600201] ; National Natural Science Foundation of China (NSFC)[U20A20202] ; National Natural Science Foundation of China (NSFC)[62090024] ; National Natural Science Foundation of China (NSFC)[61876173] ; Youth Innovation Promotion Association CAS
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Interdisciplinary Applications ; Engineering, Electrical & Electronic
WOS记录号	WOS:000976102300011
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：5[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/21444
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Mu, Jianan
作者单位	1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Processors, Beijing 100190, Peoples R China 2.Univ Chinese Acad Sci, Beijing 100190, Peoples R China 3.CASTEST, Beijing 100190, Peoples R China 4.Peking Univ, Sch Software & Microelect, Beijing 100871, Peoples R China 5.Yale Univ, Comp Architecture & Secur LAB, New Haven, CT 06511 USA 6.Open Secur Res, Shenzhen 518063, Peoples R China 7.Binary Semicond Co Ltd, Rock Solid Secur Lab, Suzhou 215000, Peoples R China 8.Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore 9.Hohai Univ, Coll Internet Things Engn, Changzhou 213022, Peoples R China
推荐引用方式 GB/T 7714	Mu, Jianan,Ren, Yi,Wang, Wen,et al. Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2023,42(5):1504-1517.
APA	Mu, Jianan.,Ren, Yi.,Wang, Wen.,Hu, Yizhong.,Chen, Shuai.,...&Li, Xiaowei.(2023).Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,42(5),1504-1517.
MLA	Mu, Jianan,et al."Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 42.5(2023):1504-1517.