JBNN: A Hardware Design for Binarized Neural Networks Using Single-Flux-Quantum Circuits

doi:10.1109/TC.2022.3215085

	JBNN: A Hardware Design for Binarized Neural Networks Using Single-Flux-Quantum Circuits
	Fu, Rongliang 1; Huang, Junying 2; Wu, Haibin 2; Ye, Xiaochun 2; Fan, Dongrui 2; Ho, Tsung-Yi 1
	2022-12-01
发表期刊	IEEE TRANSACTIONS ON COMPUTERS
ISSN	0018-9340
卷号	71 期号:12 页码:3203-3214
摘要	As a high-performance application of low-temperature superconductivity, superconducting single-flux-quantum (SFQ) circuits have high speed and low-power consumption characteristics, which have recently received extensive attention, especially in the field of neural network inference accelerations. Despite these promising advantages, they are still limited by storage capacity and manufacture reliability, making them unfriendly for feedback loops and very large-scale circuits. The Binarized Neural Network (BNN), with minimal memory requirements and no reliance on multiplication, is undoubtedly an attractive candidate for implementing inference hardware using SFQ circuits. This work presents the first SFQ-based Binarized Neural Network inference accelerator, namely JBNN, with a new representation to binarize weights and activation variables. Every SFQ gate is essentially a pipeline stage, making conventional design methods of the accumulator unsuitable for SFQ circuits. So an SFQ-based accumulative parallel counter using SFQ logic cells including T1, OR, and AND is designed to realize the accumulation, where the data size is reduced to a quarter after passing the XNOR column and the AU layer, largely declining the hardware cost. Our evaluation shows that the proposed design outperforms a cryogenic CMOS-based BNN accelerator design running at 77K by 70.92 times while maintaining 97.89% accuracy on the MNIST benchmark dataset. Without the cooling cost, the power efficiency increases up to 929.18 times.
关键词	Superconducting single-flux-quantum accelerator binarized neural network
DOI	10.1109/TC.2022.3215085
收录类别	SCI
语种	英语
资助项目	Hong Kong Jockey Club Charities Trust ; Chinese Academy of Sciences[XDA18000000] ; National Natural Science Foundation of China[61732018] ; National Natural Science Foundation of China[61872335] ; Youth Innovation Promotion Association CAS
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:000886309300012
出版者	IEEE COMPUTER SOC
引用统计	被引频次：6[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/20315
专题	中国科学院计算技术研究所期刊论文
通讯作者	Fu, Rongliang
作者单位	1.Chinese Univ Hong Kong, Dept Comp Sci & Engn, Hong Kong 999077, Peoples R China 2.Chinese Acad Sci, Inst Comp Technol, SKLP, Beijing, Peoples R China
推荐引用方式 GB/T 7714	Fu, Rongliang,Huang, Junying,Wu, Haibin,et al. JBNN: A Hardware Design for Binarized Neural Networks Using Single-Flux-Quantum Circuits[J]. IEEE TRANSACTIONS ON COMPUTERS,2022,71(12):3203-3214.
APA	Fu, Rongliang,Huang, Junying,Wu, Haibin,Ye, Xiaochun,Fan, Dongrui,&Ho, Tsung-Yi.(2022).JBNN: A Hardware Design for Binarized Neural Networks Using Single-Flux-Quantum Circuits.IEEE TRANSACTIONS ON COMPUTERS,71(12),3203-3214.
MLA	Fu, Rongliang,et al."JBNN: A Hardware Design for Binarized Neural Networks Using Single-Flux-Quantum Circuits".IEEE TRANSACTIONS ON COMPUTERS 71.12(2022):3203-3214.