A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver

doi:10.3390/electronics12020257

	A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver
	Li, Weijie 1; Liu, Min 1; Zheng, Xuqiang 1; Xiao, Guangxing 1; Yuan, Guojun 2,3; Hao, Qinfen 2,3; Jin, Zhi 1
	2023
发表期刊	ELECTRONICS
卷号	12 期号:2 页码:14
摘要	This paper presents a dedicated digital signal process (DSP) for four pulse amplitude modulation (PAM4) SerDes receivers. It is targeted to implement data recovery and adaptive equalization under ultra-high-speed and large channel attenuation with a small area and high power efficiency. The DSP consists of a clock data recovery (CDR), a 16-tap feed forward equalizer (FFE), a 1-tap decision feedback equalizer (DFE), and an automatic adaptation engine. An adaptive least mean square (LMS) algorithm is utilized to make the system more intelligent in calculating tap coefficients of the FFE and DFE. To address the timing limitation associated with traditional digital DFE that cannot handle large amounts of parallel data at a high speed, speculative techniques and a customized 4-to-1 multiplexer (MUX) unit are employed to remove the summation time and reduce the selection time, respectively. A first-order sigma-delta modulator is used to replace the traditional moving average to calculate average voltages, which could prominently save the hardware resources and power consumption. Additionally, the influence of input quantization resolution on the equalization ability is analyzed. Implemented in a 28-nm CMOS, the DSP could compensate for up to 33-dB loss at 100 Gb/s with a power consumption of 7.22 pJ/bit.
关键词	digital signal process (DSP) wireline transceiver feed forward equalizer (FFE) decision feedback equalizer (DFE) parallel multiplexer (MUX) adaptive least mean square (LMS) sigma-delta
DOI	10.3390/electronics12020257
收录类别	SCI
语种	英语
资助项目	Optoelectronic and Microelectronic Devices and Integration in the National Key R&D Program of China[2021YFB2206602] ; National Natural Science Foundation of China[62074162]
WOS研究方向	Computer Science ; Engineering ; Physics
WOS类目	Computer Science, Information Systems ; Engineering, Electrical & Electronic ; Physics, Applied
WOS记录号	WOS:000916860900001
出版者	MDPI
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/19984
专题	中国科学院计算技术研究所期刊论文
通讯作者	Zheng, Xuqiang
作者单位	1.Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China 2.Chinese Acad Sci, Inst Comp Technol, Beijing 100190, Peoples R China 3.Wuxi Inst Interconnect Technol, Wuxi 214105, Peoples R China
推荐引用方式 GB/T 7714	Li, Weijie,Liu, Min,Zheng, Xuqiang,et al. A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver[J]. ELECTRONICS,2023,12(2):14.
APA	Li, Weijie.,Liu, Min.,Zheng, Xuqiang.,Xiao, Guangxing.,Yuan, Guojun.,...&Jin, Zhi.(2023).A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver.ELECTRONICS,12(2),14.
MLA	Li, Weijie,et al."A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver".ELECTRONICS 12.2(2023):14.