Line-Coalescing DRAM Cache

doi:10.1016/j.suscom.2020.100449

	Line-Coalescing DRAM Cache
	Zhang, Qianlong 1; Sui, Xiufeng 2; Hou, Rui 3; Zhang, Lixin 4
	2021-03-01
发表期刊	SUSTAINABLE COMPUTING-INFORMATICS & SYSTEMS
ISSN	2210-5379
卷号	29 页码:10
摘要	Die-stacked DRAM has emerged as an effective approach to address the memory bandwidth wall as it offers much higher bandwidth than off-chip DRAM. It is typically used along with much larger off-chip DRAM to form a hybrid memory system with sufficient capacity and abundant bandwidth. Lots of research activities have been drawn to exploit the potentials of such memory systems. One of the approaches is to use Die-stacked DRAM as a cache of off-chip DRAM. Judicious mechanisms have been proposed to manage these on-chip DRAM caches with tailored line sizes, fetch sizes, replacement policies, and allocation mechanisms. One such example is Footprint Cache [16] which uses 2 KB lines but populates each line with only referenced 64B blocks to avoid transferring dead blocks. Doing so significantly reduces the traffic between on-chip DRAM and off-chip DRAM. In this paper, we propose to extend the idea of Decoupled Sector Cache [32] to the DRAM Cache by allowing multiple sparsely populated lines to be coalesced and stored in one DRAM Cache line (we call it Line-Coalescing DRAM Cache (LCDC)). Our experimental results show that LCDC can effectively increase the utilization of on-chip DRAM and provide 16.7% performance boost over prior designs. In addition, it is orthogonal with many existing DRAM Cache techniques and can work with them to increase the performance improvement to 27.5% and achieve 89.1% of the performance of an ideal DRAM Cache design.
关键词	DRAM Cache Die-stacked DRAM 3D DRAM HBM HMC
DOI	10.1016/j.suscom.2020.100449
收录类别	SCI
语种	英语
WOS研究方向	Computer Science
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Information Systems
WOS记录号	WOS:000632637700001
出版者	ELSEVIER
引用统计	被引频次：1[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/16754
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Zhang, Qianlong
作者单位	1.Univ Chinese Acad Sci, Inst Comp Technol, Chinese Acad Sci, 6 Kexueyuan South Rd Zhongguancun, Beijing 100190, Peoples R China 2.Beijing Inst Technol, 5 South St, Beijing 100081, Peoples R China 3.Chinese Acad Sci, Inst Informat Engn, Minzhuang Rd 89-A, Beijing 100093, Peoples R China 4.Chinese Acad Sci, Inst Comp Technol, 6 Kexueyuan South Rd Zhongguancun, Beijing 100190, Peoples R China
推荐引用方式 GB/T 7714	Zhang, Qianlong,Sui, Xiufeng,Hou, Rui,et al. Line-Coalescing DRAM Cache[J]. SUSTAINABLE COMPUTING-INFORMATICS & SYSTEMS,2021,29:10.
APA	Zhang, Qianlong,Sui, Xiufeng,Hou, Rui,&Zhang, Lixin.(2021).Line-Coalescing DRAM Cache.SUSTAINABLE COMPUTING-INFORMATICS & SYSTEMS,29,10.
MLA	Zhang, Qianlong,et al."Line-Coalescing DRAM Cache".SUSTAINABLE COMPUTING-INFORMATICS & SYSTEMS 29(2021):10.