A new architecture of a fast floating-point multiplier

	A new architecture of a fast floating-point multiplier
	Zhou, X; Tang, ZM
	2003
发表期刊	ADVANCED PARALLEL PROCESSING TECHNOLOGIES, PROCEEDINGS
ISSN	0302-9743
卷号	2834 页码:23-30
摘要	In this paper, a Floating-Point multiplier, supporting IEEE 754 Standard and full pipelined, is presented. A new architecture of dual-Way Multiplier is proposed. It can reduce 13.6% delay of critical path of adder tree according to full size multiplier without increasing area. The overall multiplier has a latency of 3 cycles and a throughput of 1 cycle for a single-precision or double-precision floating-point instruction. This multiplier has been verified on a FPGA and implemented in 0.18 Micron Standard Cell technology, with its frequency 384MHz and area 732902.25um(2). This architecture is compared with other architectures under the same technique, and the result shows it is effective and efficient.
关键词	floating-point multiplier processor
收录类别	SCI
语种	英语
WOS研究方向	Computer Science
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Software Engineering ; Computer Science, Theory & Methods
WOS记录号	WOS:000187420700003
出版者	SPRINGER-VERLAG BERLIN
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/13659
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Zhou, X
作者单位	Chinese Acad Sci, Comp Technol Inst, Beijing 100080, Peoples R China
推荐引用方式 GB/T 7714	Zhou, X,Tang, ZM. A new architecture of a fast floating-point multiplier[J]. ADVANCED PARALLEL PROCESSING TECHNOLOGIES, PROCEEDINGS,2003,2834:23-30.
APA	Zhou, X,&Tang, ZM.(2003).A new architecture of a fast floating-point multiplier.ADVANCED PARALLEL PROCESSING TECHNOLOGIES, PROCEEDINGS,2834,23-30.
MLA	Zhou, X,et al."A new architecture of a fast floating-point multiplier".ADVANCED PARALLEL PROCESSING TECHNOLOGIES, PROCEEDINGS 2834(2003):23-30.