Reduction of number of paths to be tested in delay testing

	Reduction of number of paths to be tested in delay testing
	Li, HW; Li, ZC; Min, YH
	2000-10-01
发表期刊	JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
ISSN	0923-8174
卷号	16 期号:5 页码:477-485
摘要	Delay testing is important for high speed ICs. The main difficulty in delay testing comes from the huge number of paths and the large percentage of delay untestable paths. Therefore, it is critical to reduce the number of paths to be tested in delay testing. This paper presents two approaches to delay testing with significant reduction of number of paths to be tested, which provide high path delay fault coverage by testing a small number of paths. In the first approach, it is necessary to sample the primary output twice, one before and another after the transition for each test pair. The second approach is by means of accurate measurement of delays of very limited number of paths. In order to make this approach feasible, the paper also introduces a new concept of path sensitization, termed single-transition sensitization, to allow direct measurement of propagation delay of those paths. The paper presents how to select the very limited number of paths, termed sample paths, and how to generate test pairs and observation times for the sample paths for the first approach. On the other hand, it is noted for the second approach that under the analytical delay model (Proc. 9th International Conf. on VLSI Design, Bangalore, India, Jan. 1996, pp. 162-165), most of the paths are delay testable, which makes the accurate measurement approach feasible. In fact, it would be very difficult to select sample paths based on single path sensitization as it was done in (IEEE Trans. on Computers, Vol. c-29, No. 3, pp. 235-248, March 1980). The paper shows that the number of sample paths is linear to the number of gates in the circuit under test, despite exponential growth in the number of single paths.
关键词	delay testing path sensitization linearly independent analytical delay model
收录类别	SCI
语种	英语
WOS研究方向	Engineering
WOS类目	Engineering, Electrical & Electronic
WOS记录号	WOS:000089239600009
出版者	KLUWER ACADEMIC PUBL
引用统计	被引频次：5[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/13346
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Li, HW
作者单位	Chinese Acad Sci, Inst Comp Technol, CAD Lab, Ctr Fault Tolerant Comp, Beijing 100080, Peoples R China
推荐引用方式 GB/T 7714	Li, HW,Li, ZC,Min, YH. Reduction of number of paths to be tested in delay testing[J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS,2000,16(5):477-485.
APA	Li, HW,Li, ZC,&Min, YH.(2000).Reduction of number of paths to be tested in delay testing.JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS,16(5),477-485.
MLA	Li, HW,et al."Reduction of number of paths to be tested in delay testing".JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 16.5(2000):477-485.