An effective memory addressing scheme for FFT processors

	An effective memory addressing scheme for FFT processors
	Ma, YT
	1999-03-01
发表期刊	IEEE TRANSACTIONS ON SIGNAL PROCESSING (IF:4.203[JCR-2017],4.705[5-Year])
ISSN	1053-587X
卷号	47 期号:3 页码:907-911
摘要	The memory organization of FFT processors is considered. The new memory addressing assignment allows simultaneous access to all the data needed for butterfly calculations. The advantage of this memory addressing scheme lies in the fact that it reduces the delay of address generation nearly by half compared to existing ones.
收录类别	SCI
语种	英语
WOS研究方向	Engineering
WOS类目	Engineering, Electrical & Electronic
WOS记录号	WOS:000078608200034
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：65[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/13286
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Ma, YT
作者单位	Chinese Acad Sci, Comp Technol Inst, Ctr High Performance Comp, Beijing, Peoples R China
推荐引用方式 GB/T 7714	Ma, YT. An effective memory addressing scheme for FFT processors[J]. IEEE TRANSACTIONS ON SIGNAL PROCESSING,1999,47(3):907-911.
APA	Ma, YT.(1999).An effective memory addressing scheme for FFT processors.IEEE TRANSACTIONS ON SIGNAL PROCESSING,47(3),907-911.
MLA	Ma, YT."An effective memory addressing scheme for FFT processors".IEEE TRANSACTIONS ON SIGNAL PROCESSING 47.3(1999):907-911.