A Novel Macro-Block Group Based AVS Coding Scheme for Many-Core Processor

doi:10.1007/s11265-010-0543-0

	A Novel Macro-Block Group Based AVS Coding Scheme for Many-Core Processor
	Wang, Zhenyu 1; Liang, Luhong 2; Yang, Guolei 1; Zhang, Xianguo 1; Sun, Jun 1; Zhao, Debin 3; Gao, Wen 1
	2011-10-01
发表期刊	JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
ISSN	1939-8018
卷号	65 期号:1 页码:129-145
摘要	Implementation of video coding systems such as H.264/AVC and AVS on multi-core and many-core platforms is attracting much attention. The slice-level parallelism is popular in parallel video coding for its simplicity and flexibility, however, the video quality loses greatly since the partitioning of slices breaks the dependency between macro-blocks, especially on multi-core or many-core platforms. To address this problem, we propose a Macro-Block Group (MBG) parallel scheme for parallel AVS coding. In the proposed scheme, video frames are equally divided into rectangular MBG regions; each MBG consists of more rows and less columns of macro-blocks than the slice-level scheme. Given that MBG is not syntactically supported by AVS, a vertical partitioning scheme is introduced. Additionally, we use mode confining and motion vector difference adjusting techniques to keep consistent with the standard. Two MBG parallel schemes (5 x 9 MBG partition and 8 x 7 MBG partition) are developed on a TILE64 many-core platform, where P/B frames use the MBG parallel scheme and I frames use the macro-block-level parallelism. Experimental results show that the proposed scheme of 5 x 9 MBG partition can achieve a reduction of 52% (IPPP) and 41% (IBBP) quality loss while keeping the same speed-up compared with the slice-level parallelism. With more cores employed, the scheme of 8 x 7 MBG partition gains 23.9 times of speed-up compared with the single-core implementation and achieves similar coding performance as the 5 x 9 scheme.
关键词	Parallel video encoding Macro-block group Many-core processor
DOI	10.1007/s11265-010-0543-0
收录类别	SCI
语种	英语
资助项目	National Basic Research Program of China (973 Program)[2009CB320902] ; National Natural Science Foundation of China[60832004] ; Beijing Municipal Natural Science Foundation[4102025]
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Information Systems ; Engineering, Electrical & Electronic
WOS记录号	WOS:000294837200011
出版者	SPRINGER
引用统计	被引频次：9[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/12791
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Wang, Zhenyu
作者单位	1.Peking Univ, Beijing 100871, Peoples R China 2.Chinese Acad Sci, Inst Comp Technol, Key Lab Intelligent Informat Proc, Beijing 100190, Peoples R China 3.Harbin Inst Technol, Harbin 150001, Peoples R China
推荐引用方式 GB/T 7714	Wang, Zhenyu,Liang, Luhong,Yang, Guolei,et al. A Novel Macro-Block Group Based AVS Coding Scheme for Many-Core Processor[J]. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY,2011,65(1):129-145.
APA	Wang, Zhenyu.,Liang, Luhong.,Yang, Guolei.,Zhang, Xianguo.,Sun, Jun.,...&Gao, Wen.(2011).A Novel Macro-Block Group Based AVS Coding Scheme for Many-Core Processor.JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY,65(1),129-145.
MLA	Wang, Zhenyu,et al."A Novel Macro-Block Group Based AVS Coding Scheme for Many-Core Processor".JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 65.1(2011):129-145.