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A flexible VLSI architecture of transport processor for an AVS HDTV decoder SoC
Zhang, Zhenrui; Wu, Di; Zhang, Peng; Xie, Don; Gao, Wen
2006-11-01
发表期刊IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
ISSN0098-3063
卷号52期号:4页码:1427-1432
摘要In this paper, we present a VLSI design of transport processor for at? A VS HDTV decoder SoC. The design provides a flexible data flow, which supports both broadcasting service and IPTV service with DVR capability. The design is characterized by two-bits architecture, in which a RISC CPU is used for control of general purpose and some dedicated hardware for accelerating data processing. The common on-chip SRAM is used to store input transport packets and the intermediate result in order to improve system performance and reduce the area. The design is described in Verilog HDL, simulated with VCS simulator, and implemented using 0.18 mu m CMOS cell library. The circuit costs about 75k equivalent logic gates and the processing capability is up to 90Mbps.(1)
关键词transport processor demultiplexing VLSI AVS
收录类别SCI
语种英语
WOS研究方向Engineering ; Telecommunications
WOS类目Engineering, Electrical & Electronic ; Telecommunications
WOS记录号WOS:000243211000042
出版者IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计
被引频次:2[WOS]   [WOS记录]     [WOS相关记录]
文献类型期刊论文
条目标识符http://119.78.100.204/handle/2XEOYT63/10652
专题中国科学院计算技术研究所期刊论文_英文
通讯作者Zhang, Zhenrui
作者单位Chinese Acad Sci, Inst Comp Technol, Beijing 100864, Peoples R China
推荐引用方式
GB/T 7714
Zhang, Zhenrui,Wu, Di,Zhang, Peng,et al. A flexible VLSI architecture of transport processor for an AVS HDTV decoder SoC[J]. IEEE TRANSACTIONS ON CONSUMER ELECTRONICS,2006,52(4):1427-1432.
APA Zhang, Zhenrui,Wu, Di,Zhang, Peng,Xie, Don,&Gao, Wen.(2006).A flexible VLSI architecture of transport processor for an AVS HDTV decoder SoC.IEEE TRANSACTIONS ON CONSUMER ELECTRONICS,52(4),1427-1432.
MLA Zhang, Zhenrui,et al."A flexible VLSI architecture of transport processor for an AVS HDTV decoder SoC".IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 52.4(2006):1427-1432.
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