High throughput and low memory access sub-pixel interpolation architecture for H.264/AVC HDTV decoder

	High throughput and low memory access sub-pixel interpolation architecture for H.264/AVC HDTV decoder
	Wang, RG; Li, M; Li, JT; Zhang, YD
	2005-08-01
发表期刊	IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
ISSN	0098-3063
卷号	51 期号:3 页码:1006-1013
摘要	In this paper, we proposed a parallel and pipeline architecture for the sub-pixel interpolation filter in H.264/AVC conformed HDTV decoder. To efficiently use the bus bandwidth, we bring forward three memory access optimization strategies to avoid redundant data transfer and improve data bus utilization. To improve the processing throughput, we use parallel and multi-stage pipeline architecture for conducting data transmission and interpolation filtering in parallel. Moreover, To balance the tradeoff between memory accessing scheme and sub-pixel interpolation processing granularity we devise a dedicated buffer organization to convert tree-structured block size reading to fixable and sequential processing. As compared to the traditional designs, our scheme offers 60% reduced memory data transfer. While clocking at 66MHz, our,design can support 1280x720@30Hz processing throughput. The proposed design is suitable for low cost and real-time applications. Moreover, it can easily be applied in system-on-chip design.
关键词	H.264 sub-pixel interpolation HDTV AVC
收录类别	SCI
语种	英语
WOS研究方向	Engineering ; Telecommunications
WOS类目	Engineering, Electrical & Electronic ; Telecommunications
WOS记录号	WOS:000232036200039
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：29[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/10211
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Wang, RG
作者单位	Chinese Acad Sci, Inst Comp Technol, Beijing 100864, Peoples R China
推荐引用方式 GB/T 7714	Wang, RG,Li, M,Li, JT,et al. High throughput and low memory access sub-pixel interpolation architecture for H.264/AVC HDTV decoder[J]. IEEE TRANSACTIONS ON CONSUMER ELECTRONICS,2005,51(3):1006-1013.
APA	Wang, RG,Li, M,Li, JT,&Zhang, YD.(2005).High throughput and low memory access sub-pixel interpolation architecture for H.264/AVC HDTV decoder.IEEE TRANSACTIONS ON CONSUMER ELECTRONICS,51(3),1006-1013.
MLA	Wang, RG,et al."High throughput and low memory access sub-pixel interpolation architecture for H.264/AVC HDTV decoder".IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 51.3(2005):1006-1013.