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Microarchitecture of the Godson-2 processor
Hu, WW; Zhang, FX; Li, ZS
2005-03-01
发表期刊JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY
ISSN1000-9000
卷号20期号:2页码:243-249
摘要The Godson project is the first attempt to design high performance general-purpose microprocessors in China. This paper introduces the microarchitecture of the Godson-2 processor which is a 64-bit, 4-issue, out-of-order execution RISC processor that implements the 64-bit MIPS-like instruction set. The adoption of the aggressive out-of-order execution techniques (such as register mapping, branch prediction, and dynamic scheduling) and cache techniques (such as non-blocking cache, load speculation, dynamic memory disambiguation) helps the Godson-2 processor to achieve high performance even at not so high frequency. The Godson-2 processor has been physically implemented on a 6-metal 0.18 mu m CMOS technology based on the automatic placing and routing flow with the help of some crafted library cells and macros. The area of the chip is 6,700 micrometers by 6,200 micrometers and the clock cycle at typical corner is 2.3 ns.
关键词superscalar pipeline out-of-order execution branch prediction register renaming dynamic scheduling non-blocking cache load speculation
收录类别SCI
语种英语
WOS研究方向Computer Science
WOS类目Computer Science, Hardware & Architecture ; Computer Science, Software Engineering
WOS记录号WOS:000227919000013
出版者SCIENCE CHINA PRESS
引用统计
被引频次:31[WOS]   [WOS记录]     [WOS相关记录]
文献类型期刊论文
条目标识符http://119.78.100.204/handle/2XEOYT63/10181
专题中国科学院计算技术研究所期刊论文_英文
通讯作者Hu, WW
作者单位Chinese Acad Sci, Comp Technol Inst, Beijing 100080, Peoples R China
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GB/T 7714
Hu, WW,Zhang, FX,Li, ZS. Microarchitecture of the Godson-2 processor[J]. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,2005,20(2):243-249.
APA Hu, WW,Zhang, FX,&Li, ZS.(2005).Microarchitecture of the Godson-2 processor.JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY,20(2),243-249.
MLA Hu, WW,et al."Microarchitecture of the Godson-2 processor".JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 20.2(2005):243-249.
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